MK1491-06 cs5530 geode clock source mds 1491-06 f 1 revision 101700 printed 11/15/00 integrated circuit systems, inc. ?525 race street ?san jose ?ca ?95126 ?(408)295-9800tel ?www.icst.com block diagram description features the MK1491-06 is a low cost, low jitter, high performance clock synthesizer for national semiconductor cs5530 based computer and portable appliance applications. using patented analog phase-locked loop (pll) techniques, the device accepts a 14.318 mhz crystal input to produce multiple output clocks. it provides selectable pci local bus and ac97 audio clocks, 24 mhz and 48 mhz clocks for super i/o and usb, as well as multiple reference outputs. the device has multiple power down modes to reduce power consumption. ?packaged in 28 pin, 300 mil wide soic or in 28 pin, 150 mil wide ssop ?provides all critical timing for the national semiconductor cs5530 geode companion chip ?four pci clocks ?selectable pcif on up to 2 outputs ?early pci clock selectability ?up to 4 reference clocks ?48 mhz usb and 24mhz sio support ?ac97 audio clock ?multiple power down modes ?low emi enable pin reduces emi radiation on pci clocks (patented) ?3.3 v ?% operation crystal oscillator vdd gnd pci clocks pcistp# 14.31818 mhz crystal output buffer output buffer audio clock xi xo pwrdwn# 14.3m/24m select 16.934 mhz or 24.576 mhz or 49.152 mhz 48 mhz low emi enable output buffers 14.318 mhz 14.318 mhz or 24 mhz output buffer slow# pcif function enable 3 audio select mux output buffers pci 3 fixed clocks early pci enable 5 6 pci frequency select 2 output buffer epci/pci
MK1491-06 cs5530 geode clock source mds 1491-06 f 2 revision 101700 printed 11/15/00 integrated circuit systems, inc. ?525 race street ?san jose ?ca ?95126 ?(408)295-9800tel ?www.icst.com pin # name type description 1, 9, 14 vdd p connect to +3.3v. must be same voltage on all pins. 2 xi i crystal connection. connect to a 14.31818 mhz crystal or input clock. 3 xo o crystal connection. connect to a 14.31818 mhz crystal, or leave unconnected for clock. 4, 7, 11, 17, 23 gnd p connect to ground. 5 14.3m(ts) ti/o 14.318 mhz output. input control for all clocks per table above. 6 14.3m o 14.318 mhz buffered reference clock output. 8 14.3m(sel audio) ti/o 14.318 mhz output and audio frequency select input per table above. 10 slow# i pci normal or slow mode select input per table on page 4. 12 fs i frequency select for pci clocks per table above. 13 sel24 i fixed frequency select input per table above. selects frequency on pin 19. 15 pwrdwn# i power down control; defined in table on page 4. 16 pcistp# i pci stop power down control; defined in table on page 4. 18, 20, 26 vdd p connect to +3.3v. must be same voltage on all pins. 19 24m/14.3m o fixed frequency clock output per table above. 21 48(le#) i/o fixed frequency clock output and low emi (spread spectrum) enable input per table above. 22 pci(epci#) i/o pci output clock that can be early. input control for early pci per table above. 24 pci o pci output clock. pci/pcif control set by pen per table above. 25 pci o pci output clock. pci/pcif control set by pen per table above. 27 pci o pci output clock. 28 ac97 audio(pen) ti/o audio clock output and pcif function enable per table above. pin descriptions pci frequency select table pin assignment 1 8 9 2 3 4 5 6 7 10 11 12 13 14 16 15 20 17 18 19 25 24 23 22 21 26 27 28 vdd gnd 14.3m xo vdd 14.3m(ts) slow# 14.3m(sel audio) xi gnd vdd gnd sel24 fs 24m/14.3m frequency select table epci# pci (pin 22) 0 1 ns early 1 normal early pci control table sel24 24m/14.3m 0 14.31818 mhz 1 24.0 mhz emi control le# pci low emi 0 on 1 off key: i = input, ti = tri-level input, o = output, p = power supply connection, (t)i/o = input on power up, becomes an output after 10ms. weak internal pull-up resistors are present on sel24, epci#, fs, le#, pcistp#, and slow#. these pins should be tied to vdd or gnd, and not be left floating. internal resistors on pen, sel audio, and ts pull to a mid-level (m). sel audio ac97 audio 0 16.9344 mhz m 24.576 mhz 1 49.152 mhz ac97 audio frequency select vdd pci(epci#) gnd vdd ac97 audio(pen) 24m/14.3m 48m(le#) pci pci pwrdwn# vdd pcistp# gnd pci pen pin 25 pin 24 0 pci pci m pci pcif 1 pcif pcif pcif enable control ts fs pci 0 0 tristate all clocks 0 1 reserved m 0 30 mhz m 1 33.3 mhz 1 0 25 mhz 1 1 37.5 mhz pcif continues to run in pci stop mode. see table on page 4. spread direction is down..
MK1491-06 cs5530 geode clock source mds 1491-06 f 3 revision 101700 printed 11/15/00 integrated circuit systems, inc. ?525 race street ?san jose ?ca ?95126 ?(408)295-9800tel ?www.icst.com electrical specifications parameter conditions minimum typical maximum units absolute maximum ratings (note 2) absolute maximum ratings (note 2) supply voltage, vdd referenced to gnd 7 v inputs and clock outputs referenced to gnd -0.5 vdd+0.5 v ambient operating temperature 0 70 ? soldering temperature max of 10 seconds 260 ? storage temperature -65 150 ? dc characteristics (vdd = 3.3v unless noted) dc characteristics (vdd = 3.3v unless noted) operating voltage, vdd 3.1 3.3 3.45 v input high voltage, vih 2 v input mid-level voltage, vim 1.2 1.4 1.6 v input low voltage, vil 0.8 v output high voltage, voh ioh=-8ma 2.4 v output low voltage, vol iol=8ma 0.4 v output high voltage, voh ioh=-8ma vdd-0.4 v operating supply current, idd no load, 33.3 mhz 30 ma power down mode supply current 15 ma short circuit current, single output driver vdd=3.3v ?0 ma input capacitance 7 pf ac characteristics (vdd = 3.3v unless noted) ac characteristics (vdd = 3.3v unless noted) input frequency 14.31818 mhz output clock rise time 0.8 to 2.0v 1.5 ns output clock fall time 2.0 to 0.8v 1.5 ns output clock duty cycle, all mhz clocks at 1.5v 45 49 to 51 55 % pci output to output skew rising edges at 1.5v 500 ps skew of epci with respect to pci 1 ns cycle to cycle jitter, pci clocks 250 ps emi reduction, peaks of 5th - 19th odd harmonics 33.3 mhz pci clock 6 11 db power up time, pwrdwn# high to all clocks stable 8 20 ms power on time, applied vdd to all clocks stable 12 25 ms note: stresses beyond those listed under absolute maximum ratings could cause permanent damage to the device. prolonged exposure to levels above the operating limits but below the absolute maximums may affect device reliability.
MK1491-06 cs5530 geode clock source mds 1491-06 f 4 revision 101700 printed 11/15/00 integrated circuit systems, inc. ?525 race street ?san jose ?ca ?95126 ?(408)295-9800tel ?www.icst.com key: 1 = connected to vdd, 0 = connected to ground, x = any valid logic level, combination input/outputs should be connected to vdd or ground through a 10 k w resistor as shown below. power down control table pcistp# pwrdwn# slow# mode pci pcif 24/14.3 14.3 description x 0 x power down low low low low all outputs low. plls and oscillator off. 0 1 x pci stop low on on on pci clocks synchronously enter and leave low state. 1 1 x on on on on on all clocks on. power-on default conditions input pin# function default condition 5 ts m all outputs enabled. 8 sel audio m audio clock (pin 28) set to 24.576 mhz 10 slow# 1 pci clocks set to 33.3 mhz. refer to power down control table above. 12 fs 1 pci frequency = 33.3 mhz. 13 sel24 1 24m/14.3m (pin 19) set to 24 mhz. 15 pwrdwn# 1 all clocks running. 16 pcistp# 1 pci clocks running. 21 le# 1 low emi function off 22 epci# 1 pin 22 set to normal pci signal (not early). 28 pen m pci (pin 25) set to pci clock (33.33 mhz). pci (pin 24) set to pcif clock (33.33 mhz). external components the MK1491-06 requires some inexpensive external components for proper operation. decoupling capacitors of 0.1? should be connected on each vdd pin to ground, as close to the MK1491-06 as possible. a series termination resistor of 33 w may be used for each clock output. see the discussion below for other external resistors required for proper i/o operation. the 14.3 mhz oscillator has internal caps that provide the proper load for a parallel resonant crystal with c l =18 pf. for tuning with other values of c l , the formula 2*(c l -18) gives the value of each capacitor that should be connected between x1 and ground and x2 and ground. i/o structure the MK1491-06 provides more functionality in a 28 pin package by using a unique i/o technique. the device checks the status of all i/o pins during power-up and at exit from the power down state. this status (pulled high, low, or mid-level) then determines the frequency selections and power down modes (see the tables on pages 2 and 4). within 10ms after power up, the inputs change to outputs and the clocks start up. in the diagrams to the right, the 33 w resistors are the normal output termination resistors. the 10k w resistor pulls low to generate a logic zero. weak internal pull-up resistors are present on sel24, epci#, fs, le#, pcistp#, and slow#. these pins should be connected directly to vdd or gnd if not under active control. internal resistors on pen, sel audio, and ts pull to a mid-level (m). to load* i/o for select = 0 (low) 10k w don? stuff for ??selection 33 w *note: do not use a ttl load. this will overcome the 10 k w pulldown and force the input to a logic 1.
MK1491-06 cs5530 geode clock source mds 1491-06 f 5 revision 101700 printed 11/15/00 integrated circuit systems, inc. ?525 race street ?san jose ?ca ?95126 ?(408)295-9800tel ?www.icst.com b d e h e a1 c a h x 45 l index area 1 2 28 pin soic inches inches millimeters millimeters symbol min max min max a -- 0.104 -- 2.65 a1 0.0040 -- 0.10 -- b 0.013 0.020 0.33 0.51 c 0.007 0.013 0.18 0.33 d 0.697 0.724 17.70 18.39 e 0.291 0.299 7.40 7.60 e .050 bsc .050 bsc 1.27 bsc 1.27 bsc h 0.394 0.419 10.01 10.64 h 0.01 0.029 0.25 0.74 l 0.016 0.050 0.41 1.27 package outline and package dimensions ( for current dimensional specifications, see jedec publication no. 95.)
MK1491-06 cs5530 geode clock source mds 1491-06 f 6 revision 101700 printed 11/15/00 integrated circuit systems, inc. ?525 race street ?san jose ?ca ?95126 ?(408)295-9800tel ?www.icst.com while the information presented herein has been checked for both accuracy and reliability, ics assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. ordering information geode is a trademark of national semiconductor corporation part/order number marking low emi feature package temperature MK1491-06r MK1491-06r yes 28 pin ssop 0 to 70? MK1491-06rtr MK1491-06r yes add tape & reel 0 to 70? MK1491-06s MK1491-06s yes 28 pin soic 0 to 70? MK1491-06str MK1491-06s yes add tape & reel 0 to 70? b d e1 e e a1 c a l index area 1 2 28 pin ssop inches inches millimeters millimeters symbol min max min max a 0.053 0.069 1.35 1.75 a1 0.004 0.010 0.10 0.25 b 0.008 0.012 0.20 0.30 c 0.007 0.010 0.19 0.25 d 0.386 0.394 9.80 10.01 e .025 bsc .025 bsc 0.65 bsc 0.65 bsc e 0.228 0.244 5.79 6.20 e1 0.150 0.157 3.81 3.99 l 0.016 0.050 0.41 1.27 package outline and package dimensions ( for current dimensional specifications, see jedec publication no. 95.)
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